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up7537 1 up7537-ds-f0200, mar. 2013 www.upi-semi.com dual-input triple-output power multiplexer for usb high side switch ? ? ? ? ? compliant to usb specifications ? ? ? ? ? operating range: 4.5 v to 5.5 v ? ? ? ? ? output voltage switch to 5vsb at s3/s4/s5 ? ? ? ? ? 200ma continuous load current ? ? ? ? ? typical 400m high side switch ? ? ? ? ? output voltage switch to 5vcc at s0/s1/s2 ? ? ? ? ? 1.2a continuous load current ? ? ? ? ? typical 80m high side switch ? ? ? ? ? low quiescent current: 100ua typical ? ? ? ? ? slow turn on and fast turn off ? ? ? ? ? enable active-high ? ? ? ? ? ul approved : e338429 ? ? ? ? ? tuv en60950-1 certification ? ? ? ? ? cb iec60950-1 certification ? ? ? ? ? rohs compliant and halogen free the up7537 is a current limited, dual-input triple-output power multiplexer acting as a high side switch for usb applications where heavy capacitive loads and short-circuits are likely to be encountered. it switches output voltages to 5vsb at s3/s4/s5 states with typical 400m switches and 200ma capacity; to 5vcc at s0/s1/s2 states with typical 80m switches and 1.2a capacity. the outputs can be parallelled to provide totally 3.0a output current at s0/ s1/s2 states. optimal switch logic according to s3# and 5vcc status ensures seamless output voltage transition. when the output load exceeds the current-limit threshold or a short is present, the up7537 asserts over current protection and limits the output current to a safe level by driving the power switches into saturation mode. other features include soft-start to limit inrush current during plug-in, thermal shutdown to prevent catastrophic switch failure from high-current loads, under-voltage lockout (uvlo) to ensure that the device remains off unless there is a valid input voltage present. the up7537 is available in psop-8l package. ? ? ? ? ? notebook and desktop pcs ? ? ? ? ? usb power management ? ? ? ? ? acpi power distribution ? ? ? ? ? hot-plug power supplies r e b m u n r e d r oe p y t e g a k c a pg n i k r a m p o t 8 u s a 7 3 5 7 p u l 8 - p o s p 8 a 7 3 5 7 p u 8 u s b 7 3 5 7 p u8 b 7 3 5 7 p u general description a pplications ordering information features note: upi products are compatible with the current ipc/ jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. 1 2 3 45 6 7 8 s3# en 5vcc gnd 5vsb vout2 vout1 up7537bsu8 vout3 9 gnd pin configuration 1 2 3 45 6 7 8 s3# 5vcc 5vcc gnd 5vsb vout2 vout1 UP7537ASU8 vout3 9 gnd
up7537 2 up7537-ds-f0200, mar. 2013 www.upi-semi.com e m a n n i pn o i t c n u f n i p # 3 s . n i p l o r t n o c e t a t s p e e l s . n o i t a r u g i f n o c g n i h c t i w s e h t s l o r t n o c s u t a t s c c v 5 e h t h t i w g n o l a n i p s i h t n e . e l b a n e p i h c . s e g a t l o v t u p t u o e h t s e l b a n e h g i h c i g o l c c v 5 . c c v 5 m o r f t u p n i y l p p u s t n e r r u c t u p t u o s e i l p p u s t a h t n i a r d t e f s o m l e n n a h c - n e h t s i n i p s i h t f u 0 1 m u m i n i m a h t i w n i p s i h t s s a p y b . c c v 5 o t d e t c e n n o c e b d l u o h s d n a s e t a t s 2 s / 1 s / 0 s t a . d n u o r g o t s r o t i c a p a c d n g . d n u o r g b s v 5 . t u p n i y l p p u s 5 s / 4 s / 3 s t a t n e r r u c t u p t u o s e i l p p u s t a h t n i a r d t e f s o m l e n n a h c - n e h t s i n i p s i h t . e c i v e d e h t r o f t n e r r u c g n i t a r e p o s e i l p p u s o s l a n i p s i h t . b s v 5 o t d e t c e n n o c e b d l u o h s d n a s e t a t s . d n u o r g o t r o t i c a p a c f u 0 1 m u m i n i m a h t i w n i p s i h t s s a p y b 3 t u o v . 3 e g a t l o v t u p t u o a h t i w n i p s i h t s s a p y b . s e c r u o s t e f s o m l e n n a h c - n m o r f t u p t u o s i n i p s i h t . d n u o r g o t r o t i c a p a c f u 0 1 m u m i n i m 2 t u o v . 2 e g a t l o v t u p t u o a h t i w n i p s i h t s s a p y b . s e c r u o s t e f s o m l e n n a h c - n m o r f t u p t u o s i n i p s i h t . d n u o r g o t r o t i c a p a c f u 0 1 m u m i n i m 1 t u o v . 1 e g a t l o v t u p t u o a h t i w n i p s i h t s s a p y b . s e c r u o s t e f s o m l e n n a h c - n m o r f t u p t u o s i n i p s i h t . d n u o r g o t r o t i c a p a c f u 0 1 m u m i n i m functional pin description typical application circuit v out1 up7537b s3# 5v cc vout1 vout2 vout3 5vsb s3# en 5vcc gnd v out3 v out2 5v sb
up7537 3 up7537-ds-f0200, mar. 2013 www.upi-semi.com functional block diagram 5vcc uvlo 5vsb uvlo thermal shutdown switch logic charge pump & current limit switch logic charge pump & current limit switch logic charge pump & current limit 5vsb vout2 vout1 vout3 5vcc s3# gnd q1 q2 q4 q3 q6 q5 en
up7537 4 up7537-ds-f0200, mar. 2013 www.upi-semi.com the up7537 is a current limited, dual-input triple-output power multiplexer acting as a high side switch for usb applications where heavy capacitive loads and short-circuits are likely to be encountered. it switches output voltages to 5vsb at s3/s4/s5 states with typical 400m switches and 200ma capacity; to 5vcc at s0/s1/s2 states with typical 80m switches and 1.2a capacity. the outputs can be parallelled to provide totally 3.0a output current at s0/ s1/s2 states. optimal switch logic according to s3# and 5vcc status ensures seamless output voltage transition. when the output load exceeds the current-limit threshold or a short is present, the up7537 asserts over current protection and limits the output current to a safe level by driving the power switches into saturation mode. other features include soft-start to limit inrush current during plug-in, thermal shutdown to prevent catastrophic switch failure from high-current loads, under-voltage lockout (uvlo) to ensure that the device remains off unless there is a valid input voltage present. the up7537 is available in psop-8l package. power switches each output contains two n-channel mosfets q1/q3/ q5 and q2/q4/q6 as power switches that supply output current to vout pins. the sources of q1/q3/q5 and q2/ q4/q6 are connected together to the vout1/vout2/vou3 respectively, the drain of q1/q3/q5 are connected to 5vcc pins and the drain of q2/q4/q6 are connected to 5vsb pin. the mosfets are without body diode and prevent current flows when turned off. q2/q4/q6 are typical 400m mosfets with 200ma capacity and q1/q3/q5 are typical 80m mosfets with 1.2a capacity. the power switches are driven by internal charge pumps and controlled by s3# and 5vcc status. the up7537 switches the output voltages to 5vsb through q2/q4/q6 at s3/s4/s5 states, to 5vcc through q1/q3/ q5 at s0/s1/s2 states. charge pumps and drivers an internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the mosfet above the source. the driver controls the gate voltage of the power switch. to limit large current surges and reduce the associated electromagnetic interference (emi) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. chip enable and soft start pulling the en pin lower than 0.4v disables the output voltages and reduces its quiescent current down to 1ua typically. pulling the en pin higher than 1.4v enables the output voltages. the up7537 features soft start function to eliminate the inrush current into downstream and voltage droop of upstream wh en hot-plug-in with capacitive loads. the soft start interval is 1.3ms typically. the input current to charge up the load capacitor is proportional to its capacitance. the up7537 current limit function may active during the plug-in of extreme large capacitive load. functional description figure 1. typical timing diagram 5vsb en 5vsb _drv vout s3# 5vcc 5vcc _drv t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
up7537 5 up7537-ds-f0200, mar. 2013 www.upi-semi.com over current limit the up7537 continuously monitors the output current for over current protection to protect the system power, the power switch, and the load from damage during output short circuit or soft start interval. when an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. the driver in turn reduces the gate voltage and drives the power fet into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. undervoltage lockout a voltage sense circuit monitors the input voltage. when the input voltage is below approximately 4.3v, a control signal turns off the power switch. overtemperature protection the up7537 continuously monitor the operating temperature of the power switch for overtemperature protection. the up7537 asserts overtemperature and turns off the power switch to prevent the device from damage if the junction temperature rises to approximately 135 o c due overcurrent or short-circuit conditions. hysteresis is built into the thermal sense, the switch will not turns back on until the device has cooled approximately 20 degrees. if the fault condition is not removed, the switch will pulse on and off as the temperature cycles between these limits. functional description
up7537 6 up7537-ds-f0200, mar. 2013 www.upi-semi.com (5v sb = 5v, t a = 25 o c, unless otherwise specified) (note 1) supply input voltage, 5vsb ----------------------------------------------------------------------------------------------- -0.3v to +5.7v supply input voltage, 5vsb compliant with lps (limited power source) requirement --------------------------- < 8a/100va other pins ------------------------------------------------------------------------------------------------------------------------------- ------ -0.3v to +5.7v storage temperature range ----------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------- ----- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 200v package thermal resistance (note 3) psop-8l ja ------------------------------------------------------------------------------------------------------------------------------ 50 o c/w psop-8l jc ------------------------------------------------------------------------------------------------------------------------------ 5 o c/w power dissipation, p d @ t a = 25 o c psop-8l ----------------------------------------------------------------------------------------------------------------------- ------------------- 2.0w (note 4) operating junction temperature ra nge ------------------------------------------------------------------------ -40 o c to +125 o c operating ambient temperature ra nge -------------------------------------------------------------------------------------- -40 o c to +85 o c supply input voltage, 5vsb ------------------------------------------------------------------------------------------------------ +4.5v to +5.5v r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u b s v 5 t u p n i y l p p u s e g n a r e g a t l o v t u p n i y p p u s 5 . 4- -5 . 5v t u o k c o l e g a t l o v r e d n uv o l v u g n i s i r b s v 5- -3 . 45 . 4v s i s e r e t s y h o l v u - -0 0 2- -v m t n e r r u c t n e c s e i u qi q v 0 = c c v 5 , 0 = # 3 s , x t u o v n o d a o l o n- -0 0 10 5 1a u t n e r r u c t n e c s e i u qi q v 5 = c c v 5 = # 3 s , x t u o v n o d a o l o n- -0 0 20 0 3a u t n e r r u c n w o d t u h si n d h s . v 5 = c c v 5 = # 3 s , v 0 = n e- -15a u c c v 5 t u p n i y l p p u s e g n a r e g a t l o v t u p n i y l p p u s 5 . 4- -5 . 5v t u o k c o l e g a t l o v r e d n uv o l v u g n i s i r c c v 5- -3 . 45 . 4v s i s e r e t s y h o l v u - -0 0 2- -v m a bsolute maximum ratin g thermal information recommended operation conditions electrical characteristics
up7537 7 up7537-ds-f0200, mar. 2013 www.upi-semi.com note 1. stresses beyond those listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in the r ecommended operation condition section of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. electrical characteristics r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u ) 6 q / 4 q / 2 q ( b s v 5 r o f h c t i w s r e w o p e c n a t s i s e r n o t e f s o m - nr ) n o ( s d i t u o 5 2 @ a m 0 0 2 = o c- -0 0 40 0 5m t n e r r u c e g a k a e l e s r e v e rv t u o v 0 = b s v 5 , v 5 . 5 =- -- -1a u ) 5 q / 3 q / 1 q ( c c v 5 r o f s e h c t i w s r e w o p e c n a t s i s e r n o t e f s o m - nr ) n o ( s d i t u o 5 2 @ a 1 = o c- -0 80 0 1m t n e r r u c e g a k a e l e s r e v e rv t u o v 0 = c c v 5 , v 5 . 5 =- -- -1a u t i m i l t n e r r u c 6 q / 4 q / 2 q r o f d l o h s e r h t t i m i l t n e r r u c 4 . 0- -- -a 5 q / 3 q / 1 q r o f d l o h s e r h t t i m i l t n e r r u c 2 . 20 . 38 . 3a t r a t s t f o s e m i t p u p m a r e g a t l o v t u p t u o c , v 0 = # 3 s t u o d a o l o n , f u 0 1 =- -3 . 1- -s m c , v 5 = c c v 5 = # 3 s t u o , f u 0 1 = d a o l o n - -3 . 1- -s m t u p n i # 3 s h g i h t u p n iv h i 4 . 1- -- -v w o l t u p n iv l i - -- -4 . 0v e m i t y a l e d h g i h o t w o l # 3 st h l - -0 1- -s m e m i t y a l e d w o l o t h g i h # 3 st l h - -0 3- -s u t u p n i n e h g i h t u p n iv h i 4 . 1- -- -v w o l t u p n iv l i - -- -4 . 0v e m i t y a l e d h g i h o t w o l n et h l - -0 5 1- -s u n o i t c e t o r p e r u t a r e p m e t r e v o l e v e l d l o h s e r h t n w o d t u h s l a m r e h tn g i s e d y b- -5 3 1- - o c s i s e r e t s y h n w o d t u h s l a m r e h tn g i s e d y b- -0 3- - o c
up7537 8 up7537-ds-f0200, mar. 2013 www.upi-semi.com v out1 (2v/div) en (2v/div) v out1 (2v/div) en (2v/div) v out1 (2v/div) 5vsb (2v/div) s3# (2v/div) 5vcc (2v/div) typical operation characteristics v out1 (2v/div) 5vsb (2v/div) v out1 (2v/div) 5vsb (2v/div) 5vcc (2v/div) v out1 (2v/div) 5vsb (2v/div) s3# (2v/div) 5vcc (2v/div) power on by 5vsb time (4ms/div) c out1 = 10uf, s3# = 0v power on by 5vcc time (4ms/div) c out = 10uf, 5vsb = s3# = 5v, 5vcc = 4.5v s3# from high to low time (100us/div) 5vsb = 4.5v, 5vcc = 5.5v, c out1 = 10uf s3# from low to high time (2ms/div) 5vsb = 4.5v, 5vcc = 5.5v, c out1 = 10uf turn on with s3# = low time (400us/div) 5vsb = 5v, c out1 = 10uf, i out1 = 100ma turn on with s3# = high time (400us/div) 5vsb = 5vcc = 5v, c out1 = 10uf, i out1 = 100ma
up7537 9 up7537-ds-f0200, mar. 2013 www.upi-semi.com v out (2v/div) i out (2a/div) v out (2v/div) i out (500ma/div) 0 100 200 300 400 500 600 -50 0 50 100 150 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 -50 0 50 100 150 en/s3# falling en/s3# rising 4 4.05 4.1 4.15 4.2 4.25 4.3 4.35 4.4 -50 0 50 100 150 5vsb/5vcc falling 5vsb/5vcc rising typical operation characteristics por threshold level vs. temperature junction temperature ( o c) por threshold level (v) control input level vs. temperature junction temperature ( o c) control input threshold level (v) q2/q4/q6 on resistance vs. temperature junction temperature ( o c) q2/q4/q6 on resistance (m ) ocp for 5vsb ocp for 5vcc time (400us/div) c out = 10uf, s3# = 0v time (400us/div) c out = 10uf, s3# = 5v 0 20 40 60 80 100 120 140 -50 0 50 100 150 q1/q3/q5 on resistance vs. temperature junction temperature ( o c) q1/q3/q5 on resistance (m )
up7537 10 up7537-ds-f0200, mar. 2013 www.upi-semi.com 0 40 80 120 160 200 -50 0 50 100 150 quiescent current vs. temperature junction temperature ( o c) s3# = 5vcc = 0v. quiescent current (ua) typical operation characteristics
up7537 11 up7537-ds-f0200, mar. 2013 www.upi-semi.com a pplication information the up7537 is a current limited, dual-input triple-output power multiplexer acting as a high side switch for usb applications where heavy capacitive loads and short-circuits are likely to be encountered. it switches output voltages to 5vsb at s3/s4/s5 states with typical 400m switches and 200ma capacity; to 5vcc at s0/s1/s2 states with typical 80m switches and 1.2a capacity. the outputs can be parallelled to provide totally 3.0a output current at s0/ s1/s2 states. optimal switch logic according to s3# and 5vcc status ensures seamless output voltage transition. when the output load exceeds the current-limit threshold or a short is present, the up7537 asserts over current protection and limits the output current to a safe level by driving the power switches into saturation mode. other features include soft-start to limit inrush current during plug-in, thermal shutdown to prevent catastrophic switch failure from high-current loads, under-voltage lockout (uvlo) to ensure that the device remains off unless there is a valid input voltage present. the up7537 is available in psop-8l package. input and output capacitors bypass the supply input pins with a single 4.7uf capacitor as close as possible to the up7537. a 4.7uf output capacitor at the output pin is recommended even much larger output capacitors are already available at the output of the up7537, especially if the output capacitors are more than 2 inches away on the pcb. the inrush current to charge the output capacitors is calculated as: ss out out in t v c i = (a) special care should be paid to large output capacitor applications. take c out = 1000uf as example, the inrush current is i in = 1000uf x 5v / 1.3ms = 3.8a. this is higher than the current limit threshold of q1/q3/q5 and q2/q4/ q6. in this case, the output voltage ramp up time is controlled by the current limit function of q1/q3/q5 and q2/q4/q6 as shown in figure 1. note that output voltage ramping up slew rates are different due to different outupt capacitors. time: 4ms/div v out1 (2v/div) i out2 (1av/div) 5vsb (2v/div) v out2 (2v/div) figure 1. turn on into 5vsb c out2 = 1500uf, c out1 = 10uf. the output voltage undergoes an abrupt drop when a device with large input capacitors is hot plugged into the output of up7537 as shown in figure 2, where a device with 1500uf is hot plugged into up7537 output with 470uf output capacitor. the output voltage ramp up time is controlled by the current limit level. time: 4ms/div v out1 (2v/div) i out2 (1av/div) v out2 (2v/div) figure 2. hot plug application with s3# = 0v.
up7537 12 up7537-ds-f0200, mar. 2013 www.upi-semi.com a pplication information thermal consideration temperature effect should be well considered when dealing with voltage drop and power dissipation. the maximum r ds(on) of the power switch is 80m of q1/q3/q5 under 25 o c junction temperature. if the device is expected to operate at 125 o c junction temperature, the r ds(on) of q1/ q3/q5 will become 80m * (1 + (125 o c - 25 o c) * 0.5%/ o c) = 120m where 0.5%/ o c is the approximated temperature coefficient of the r ds(on). if the maximum load current is expected to be 1.2a, the maximum voltage will become 1.2a * 120m = 144mv this in turn will cause power dissipation as 1.2a * 144mv = 173mw the temperature raise is calculated as 173mw * 50 o c/w = 8.7 o c the junction temperature is calculated as t a + 8.7 o c, where t a is the expected maximum ambient temperature. a few iterations are required until get final solutions. the thermal resistance ja highly depends on the pcb design. copper plane under the exposed pad is an effective heatsink and is useful for improving thermal conductivity. figure 3 show the relationship between thermal resistance ja vs. copper area on a standard jedec 51-7 (4 layers, 2s2p) thermal test board at t a = 25 o c. a 50mm 2 copper plane reduces ja from 75 o c/w to 50 o c/w and increases maximum power dissipation from 1.33w to 2w. 60 70 50 40 30 20 10 0 60 70 50 40 30 90 100 80 t hermal resi stanc e ja ( o c/w) copper area (mm 2 ) figure 3. thermal resistance ja vs. copper area pcb layout consideration ? ? ? ? ? place the up7537 as close to the usb connector as possible to minimize the parasitic elements. ? ? ? ? ? place local bypass capacitors as closed as possible to the 5vsb and 5vcc pins. use short and wide traces to minimize parasitic resistance and inductance. ? ? ? ? ? the exposed pad should be soldered on gnd plane with maximum area and with multiple vias to inner layer of ground place for improved thermal performance. ? ? ? ? ? keep the power trace short and wide to minimize the parasitic resistance along the trace.
up7537 13 up7537-ds-f0200, mar. 2013 www.upi-semi.com note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. package information psop - 8l 0.31 - 0.51 4.80 - 5.00 5.79 - 6.20 0.10 - 0.25 0.40 - 1.27 1.27 bsc 3.80 - 4.00 1.80 - 2.40 1.80 - 2.40 0.00 - 0.15 1.7 max 1
up7537 14 up7537-ds-f0200, mar. 2013 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. however, no res ponsibility is assumed by upi or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2009, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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